6 / 10 TLB

The Handler Must Not Fault

On a software-managed TLB (MIPS R10k, SPARC v9) the hardware's job on a miss is one line:

1  VPN = (VirtualAddress & VPN_MASK) >> SHIFT
2  (Success, TlbEntry) = TLB_Lookup(VPN)
3  if (Success == True)      // TLB hit
4      ... form physical address, access memory ...
10 else                      // TLB miss
11     RaiseException(TLB_MISS)

Everything else is an OS trap handler that walks the page table and executes a privileged instruction to install the entry. What must the OS arrange so this design does not collapse the first time it is used?

A

The handler must return to the instruction following the faulting one, exactly as a system call return does, because the faulting instruction has already been retired.

B

The miss handler's own code and the page table it reads must be reachable without a translation, either by placing them in unmapped physical memory or by reserving permanently valid wired TLB entries.

C

The handler must run with interrupts disabled, so no other trap can install a conflicting entry between the lookup and the install.

D

The handler must flush the whole TLB before installing the entry, since without an address-space identifier a stale entry from the previous process could be matched.