Cycles Per Access
Core i7 hierarchy, per CS:APP: L1 data cache 32 KB 8-way at 4 cycles, L2 256 KB at 10 cycles, L3 8 MB 16-way at roughly 50 cycles, 64-byte lines.
A matrix kernel runs with a 3% L1 miss rate, and every L1 miss is satisfied by L3. Blocking the loops drops the L1 miss rate to 1%, with the same L3 behaviour.
What is the average access latency before and after?
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