Memory Hierarchy Latencies

Approximately how many CPU cycles does a main memory (DRAM) access take compared to an L1 cache hit on a modern processor?

A

They are roughly the same on modern hardware

B

L1: ~1 cycle, DRAM: ~10 cycles

C

L1: ~1-3 cycles, DRAM: ~100-200 cycles

D

L1: ~10 cycles, DRAM: ~50 cycles