Same Size Different Misses

Two caches, both holding 8 bytes of data, both with 2-byte blocks, on a machine with 4-bit addresses. Replacement is LRU.

cache	sets	lines per set	address split
X	4	1	tag 1, set 2, offset 1
Y	2	2	tag 2, set 1, offset 1

Both start empty and read these byte addresses in order: 0, 1, 7, 8, 0.

Where do the two traces diverge?

At the read of address 1, because the two caches use different block sizes.

Nowhere. Both hold 8 bytes, so both take the same number of misses; only which line holds what differs.

At the final read of address 0: it misses in X and hits in Y, because 0 and 8 fall in the same set of X and that set holds only one line.

At the read of address 7: it hits in X and misses in Y, because Y has fewer sets and 7 collides with an earlier block.