White RoomNEW

Silent Promotion

Two cores, one 64-byte line holding X. No other core caches it at the start.

step operation core 0 core 1
1 core 0 reads X E I
2 core 0 writes X M I
3 core 1 reads X S S
4 core 1 writes X I M

Select every statement that is true of this trace. More than one applies.