Grid of Multipliers

Both NVIDIA tensor cores and Google TPU MXUs accelerate matmul-heavy workloads like transformer attention and dense layers. What architectural mechanism does the TPU's systolic array use that differs from a tensor core's per-cycle small matrix multiply-accumulate approach?

The systolic array assigns one thread per output element and relies on a SIMT warp scheduler for coordination

Operands stream through a 2D grid of processing elements where each weight is loaded once and held stationary, reused across many multiply-accumulate cycles as activations flow through, cutting repeated memory reads

The systolic array performs all computation in 64-bit floating point for maximum accuracy

The systolic array eliminates on-chip memory entirely, streaming every operand directly from HBM each cycle