10 / 18 Pipelining & Execution

Superscalar Execution

A superscalar processor can issue multiple instructions per clock cycle. What limits the actual IPC (instructions per cycle) achieved in practice?

A

Memory is always the bottleneck; IPC is determined entirely by cache hit rate

B

The clock speed: faster clocks always mean higher IPC

C

Data dependencies, branch mispredictions, and resource conflicts

D

The operating system limits IPC to prevent overheating